VLF Direction Finding — Ethernet Data Acquisition
Current-code revision note This revision supersedes the older 1 MHz / TIM3-TRGO timing description. The current firmware revision was checked against main(5).c. The actual timing architecture is: PA0 / 1 MHz ──► TIM5_CH1 ──► TIM5 counter / timestamp PA3 / GNSS PPS ─────────────► TIM5_CH4 capture PA6 / 1 MHz ──► TIM3_CH1 ──► reset ──► TIM3_CC4 ──► ADC1/2/3 In particular, TIM3 TRGO is not used for the ADCs. TIM5 does not generate the ADC sampling clock; it counts a separate external 1 MHz timing signal on PA0. ...